1. Field of the Invention
The present invention relates to a microprocessor, and more specifically a microprocessor capable of ensuring a recovery time of an I/O (input/output) device in bus cycles for consecutive I/O accesses.
2. Description of Related Art
Conventional microprocessors have operated at a relative low operation frequency, and required a relatively large number of clocks, typified by three or four clocks, for each one bus cycle, so that a final clock in each bus cycle can be used for recovery. Therefore, a recovery time for a peripheral I/O control LSI is ensured and fulfilled. Accordingly, when an external bus cycle is triggered, a bus cycle similar to a memory access has been performed in an I/O access.
A typical conventional timing generator has been composed of a combinational circuit having outputs for generating a state T1 signal, a state T2 signal, a state T3 signal, a state T4 signal and an idle state Ti signal, respectively, in such a manner that only one of the five state signals is active. Five latches are provided for latching the state T1 signal, the state T2 signal, the state T3 signal, the state T4 signal and the idle state Ti signal, respectively, in synchronism with a clock. These five state signals latched in the five latches am supplied as control signals, and also fed back to the combinational circuit itself for generation of a next active state signal. The combinational circuit also receives a reset signal RESET, an access request signal ACCRQ, and a ready signal READY. For example, the combinational circuit is formed of a programmable logic array (PLA), which realizes the following state transition table 1:
TABLE 1 ______________________________________ NOW NEXT RESET ACCRQ READY ______________________________________ -- Ti 1 -- -- Ti T1 0 1 -- Ti Ti 0 0 -- T1 T2 0 -- -- T2 T3 0 -- -- T3 T3 0 -- 1 T3 T4 0 -- 0 T4 T1 0 1 -- T4 Ti 0 0 -- ______________________________________
In the above table 1, the column "NOW" indicates an active state signal currently outputted from the combination circuit, and the column "NEXT" indicates an active state signal which will be outputted from the combination circuit after a clock signal is applied.
In this example, a basic bus cycle is completed with four clocks of the state T1, the state T2, the state T3 and the state T4. As seen from the above table, if the reset signal RESET is applied, the condition enters into the idle state Ti, and the idle state Ti is repeated until the access request signal ACCRQ is applied. If the access request or the I/O access request is generated, the condition enters into the state T1. The T1 state will without exception change to the state T2, which will also without exception change to the state T3. If there exists a wait request due to the ready signal READY, the state T3 is repeated. Finally, the condition changes to the state T4 which is a last condition of the bus cycle.
For example, in consecutive I/O accesses of an I/O read bus cycle and a succeeding I/O write bus cycle on the basis of the above mentioned basic states, a recovery time corresponding to about one clock is ensured after completion of the I/O read data access until a start of acknowledgement of a next I/O write address access. If the frequency of the clock signal is 5 MHz, a period of one clock is 200 nanoseconds. Therefore, it is possible to connect an external I/O device having a recovery time not greater than 200 nanoseconds. On the other hand, since the recovery time is ensured for each bus cycle regardless of whether the access is the I/O access or the memory access, the efficiency has been low, particularly in the memory access.
Here, assuming that the same I/O device is consecutively accessed, the "recovery time" means a command recovery time after completion of execution of a first command of the I/O device until start of acknowledgement of a second command of the same I/O device. It is necessary to couple each I/O device in such a manner that the command recovery time is fulfilled or ensured.
Recent improvement of performance of the microprocessors have accompanied with the inclination of increase of the clock frequency and simplification of the bus cycle with the result that each one bus cycle is composed of only one clock or two clocks. Here, assuming that the clock frequency is 10 MHz which is sufficiently higher than 5 MHz of the conventional microprocessor, the period of one clock becomes 100 nanoseconds. This will make it impossible to ensure the recovery time when the conventional I/O device is coupled.
In addition, when the bus cycle is simplified, for example, when each one bus cycle is composed of two clocks, it becomes impossible to have the recovery time between consecutive I/O accesses. This ultimately gives an adverse effect to the memory access.